1. Field of the Invention
The present invention relates in general to multiprocessor systems including a plurality of processors having respective cache memories and a memory unit shared by at least two of the processors, and more particularly to a multiprocessor system that maintains cache coherence in response to memory access requests from the processors.
2. Discussion of the Related Art
Conventional multiprocessor systems include a plurality of processors that may share (or access) the same memories. There are two basic memory sharing techniques. In the first technique, the processors may have access to the same address areas of the same memory. And in the second technique, the processors may have access to different address areas of the same memory. It will be appreciated that when the processors have access to the same address areas of the same memory (i.e., the first technique), then data read by one processor can also be read by another processor. Here, the memory is typically referred to as a shared-memory.
Software may be implemented using several program modules. When software programs are executed, the program modules may exchange information via the shared-memory. As a result, if the program modules are carried out in parallel on different processors, it may become difficult to perform the appropriate and timely shared-memory functions (e.g. updating the shared-memory).
To reduce the average time required by the processors to access the shared-memories, one or more cache memories may be arranged between the processors and the shared-memories. In some multiprocessor systems, each of the processors may include its own local cache memory that may be separate from the shared-memories. In such systems, the caches are kept in a state of coherence by ensuring that any shared data that is changed in any cache is changed throughout the entire system. Thus, cache coherence may be considered before a write operation under the condition that the requested data block is shared by a cache memory in another processor.
Many conventional methods have been implemented to maintain cache coherence. Such conventional methods may include a write-invalidate protocol, a snooping scheme, and a directory scheme. Although such conventional methods are generally thought to provide acceptable memory sharing functions, they are not without shortcomings. For example, rather complex logic may be necessary to implement the conventional methods. Such complex logic may increase power consumption and the time required for designing the processor core.